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| mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 1 advance information ntsc digital video encoder hcmos technology mc44722 mc44723 ft suffix 48 qfp (0.8mm pitch) the mc44722 and mc44723 are digital video encoders (dve). they convert itu-601/656 standard 4:2:2 bit-paralellel data into analog composite video, s-video or y/cb/cr in pal and ntsc formats. they accept the multiplexed ((cb,y,cr)y) signals from digital sources such as mpeg decoders and can act as a sync generator master. all video processing is done digitally and requires no external adjustment. specifically designed for digital satellite, digital cable decoders and multimedia terminals. ?world wide operation (pal-bdghi, pal-n,pal-m, ntsc-m) ?smpte 170m / itu - r 624 composite video output ?programmable color sub-carrier frequencies ? analog horizontal , vertical , frame or composite sync outputs ?sync extraction from digital input data (sav, eav) ?sync polarity and horizontal phase control ?master or slave sync ( h/vsync, h/fsync, itu-r656 slave ) operation ?interlaced or non-interlaced support ?625/50 or 525/60 itu-601/656 8-bit ((cb,y,cr)y) digital input ?luma 2x / chroma 4x oversampling filtering ? external vbi information data input (such as teletext information data) ? cvbs / ys / cs or y / cb / cr analog outputs through 10-bit dacs ?easily programmed via serial bus ( i2c or spi bus) ? 2 hardware i2c chip addresses ? closed-caption and cgms information data insertion ? macrovision ver. 7.01 anti-copy signal insertion (mc44722 only support ntsc mode) ?on chip color - bar generator ? +3.3v power supply or +3.3v (digital)/ +5v (analog) power supply
?pin compatible with mc44720ft the mc44722 device is protected by u.s. patent number 4,631,603,4,577,216 and 4,819,098 and other intellectual property rights. the use of macrovision's copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited.
mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. [pin assignment] cvbs / cb hsync ext tvin dvin3 dvin4 dvin5 dvin6 dvin7 tp9 tp8 tp7 tp6 tp5 dvss dvdd tp4 mc44722 mc44723 2 1 2 3 4 5 6 7 8 9 12 14 15 16 17 18 19 20 21 vreff 13 24 22 10 11 36 35 34 33 32 31 30 29 28 25 27 26 23 47 46 45 44 43 42 41 40 48 37 39 38 cvbs / cb cvbs/cbvdd y y yvdd c / cr c / cr cvdd davss ibias davdd chipa test so sda/si scl/sck sel dvss clock dvdd reset pal/ntsc dvin0 dvin1 dvin2 f / vsync tp3 tp2 tp1 tp0 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. [pin descriptions] 1 cvbs / cb o analog composite video signal output or cb signal output current drive(positive) 2 cvbs /cb o analog composite video signal output or cb signal output current drive(negative) 3 cvbs/cbvdd power supply for cvbs / cb dac circuit 4 y o analog luminance signal output current drive(positive) 5 y o analog luminance signal output current drive(negative) 6 yvdd power supply for y dac circuit 7 c/cr o analog chrominance signal output or cr signal output current drive(positive) 8 c/cr o analog chrominance signal output or cr signal output current drive(negative) 9 c/crvdd power supply for c / cr dac circuit 10 davss ground for dac circuit 11 ibias o reference current for the 3 dacs 12 davdd power supply for dac circuit 13 vreff reference full scale voltage for the 3 dacs 14 chipa i2c chip address select { 0 : 42(hex)/43(hex) 1 : 1c(hex )/1d(hex) } 15 test i test pin(ground) 16 so z(o) if spi mode, serial data output / if i2c mode, connect to ground 17 sda/si i/o(i) serial data input, open drain output / if spi mode, serial data input 18 scl/sck i serial clock 19 sel (i) connect to ground / if spi mode, this pin is chip select 20 dvss ground for digital circuit 21 clock i 27mhz clock input 22 dvdd power supply for digital circuit 23 reset i reset signal, active low 24 pal/ntsc i ntsc/pal select . this pin active only reset time. (ntsc : low pal : high ) 25~32 dvin7~0 i 8-bit multiplexed y/cr/cb 4:2:2 data(ccir rec656) input(1) 33 tvin i test data input 34 ext i/o csync/frame sync output or external vbi information input 35 f/vsync i/o frame sync or vertical sync input/output 36 hsync i/o horizontal sync input/output 37 tp9 i/o for d/a converter test 38 tp8 i/o mux switch in 8-bit multiplexed y/cr/cb 4:2:2 data(ccir rec656) input mode, or test data input/output 39~41 tp7~5 i/o 8-bit multiplexed 4:2:2 data(ccir rec656/601) input(2), or multiplexed cr/cb data (ccir rec656/601) input in 16-bit input mode (msb : tp7), or test data input/output 42 dvss ground for digital circuit 43 dvdd power supply for digital circuit 44~48 tp4~0 i/o 8-bit multiplexed 4:2:2 data(ccir rec656/601) input(2), or multiplexed cr/cb data (ccir rec656/601) input in 16-bit input mode (lsb : tp0), or test data input/output 3 pin name i/o descriptions mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 4 dac yout yout cout / cr cout / cr cvbsout / cb cvbsout / cb yvdd cvbs/cbvdd c/crvdd davdd davss ibias bias ext f/vsync hsync dvin sda/si scl/sck 0 0 0 0 cgms_gen cc_gen sync_generator copy protection bus off_set bg modulator subcarrier gen 0 dac 0 dac 0 tp0~9 test test pal/ntsc reset tvin demux y cb cr h,v chipa dvdd dvdd dvss dvss i2c/spi chip-address 42/43(hex) 1c/1d(hex) clock [block diagram] mc44722/3 vreff sel so i2c / spi tp0~7 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 5 clock 27.0mhz is necessary. this signal on the clock pin needs to be active before the reset pin is de-asserted. ( see figures 1 and 2 ) [function descriptions] fig 1 : dvin data input timing input clock 27mhz input data dvin0~7 50% tds tdh clock 27mhz output data h/vf sync output data tp0~8 td td fig 2 : sync data output timing reset procedure reset is a level sensitive input pin. driving the reset pin low causes a dve reset. the 27mhz dve clock signal must be active before reset is released. de-asserting reset will latch the status of the pal/ ntsc, tvin and sel pins. the pal/ntsc pin determines the default values for the dve control registers. the default register values have been chosen so that standard pal or ntsc video will appear at the dac outputs immediately when a valid input digital video data stream is present. the value on the sel pins determine the default serial communication mode. if low, the dve use i2c bus operation. if high, the dve use 4-wire spi operation. after reset, the vbi signals (closed-caption and cgms) are disabled. (see page --- for sub-address register descriptions.) mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. video timing / sync generator the dve outputs pal-b,d,g,h,i, pal-n, pal-m or ntsc-m standard video signals. the dve sync generator can be operated in two modes, master or slave. in master mode, the dve generates all the correct horizontal and vertical or frame sync signals internally, or it is output csync signal through the ext pin(c/fsync). in slave mode, the dve derives the sync signals from the bit-parallel input data stream start active video (sav) and end active video (eav) data packet information. sync signals are output on the hsync and f/vsync or ext pins and can be programmed for positive or negative polarity. the phase of hsync can also be controlled. also, the dve allows more two slave modes. one is h/vsync slave, and the aother is h/fsync slave mode. vertical blanking corresponds to the following lines. 625/50 624-22 311-335 itu-r line numbering 525/60 1-19 264-282 smpte line numbering (see figures 3,4,5,6,7,8,9,10, and 11 for sub-address register descriptions.) 6 fig 3 : digital input timing(525/60 system) in master mode 1440t hsync phase sub-address71[2:0] hsync clock 124t t 242t hsync polarity sub-address71[5] +3t delay -4t delay dvin0~7 cr 718 cb 718 y 718 y 719 00 00 ff cb 2 cr 0 cb 0 y 0 y 1 y 2 invalid 00 00 xy ff 70(hex){[1:0]=01} y 718 y 719 tp0~7 cr 718 cb 718 cb 2 cr 0 cb 0 invalid dvin0~7 y2 y 1 y 0 invalid 16-bit input mode cb 718 cr 718 cr 2 cr 0 cb 0 or input data format the input digital video is in accord with the itu-r rec.656 and smpte 125m standards. it is two 8-bit or 16-bit multiplexed 4:2:2 ((cb,y,cr)y) data stream. samples are latched on the rising edge of the clock signal. data is input on pins dvin[ 7 : 0 ] and tp[ 8 : 1 ] (see figures 3 and 4 for sub-address register descriptions.) 8-bit input mode mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 7 csync csync 525 524 1 2 3 4 5 6 7 8 9 10 11 21 22 23 262 261 263 264 265 266 267 268 269 270 271 272 273 283 284 285 fig 5 : sync timing::525/60 interlaced system in master mode vsync hsync vsync hsync sub-address71[7] =0 fsync fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync fig 4 : digital input timing(625/50 system) in master mode dvin0~7 1440t cr 718 cb 718 y 718 y 719 00 00 ff cb 2 cr 0 cb 0 y 0 y 1 y 2 invalid 00 00 xy ff hsync phase sub-address71[2:0] hsync clock 124t t 262t hsync polarity sub-address71[5] +3t delay -4t delay 70(hex){[1:0]=01} y 718 y 719 tp0~7 cr 718 cb 718 cb 2 cr 0 cb 0 invalid dvin0~7 y2 y 1 y 0 invalid 16-bit input mode cb 718 cr 718 cr 2 cr 0 cb 0 or 8-bit input mode mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 8 csync 262 261 1 2 3 4 5 6 7 8 9 10 11 21 22 23 fig 7 : sync timing::525/60 non-interlaced system in master mode csync 310 311 312 1 2 3 4 6 7 8 21 22 23 5 309 308 vsync hsync vsync hsync fig 8 : sync timing::625/50 non-interlaced system in master mode 9 sub-address71[7] =1 fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync sub-address71[7] =1 csync 623 624 625 1 2 3 4 6 7 8 21 22 23 csync 311 312 313 314 315 316 317 318 319 320 321 334 335 5 622 621 310 309 vsync hsync vsync hsync fig 6 : sync timing::625/50 interlaced system in master mode 9 fsync fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync sub-address71[7] =0 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. fig 10 : sync timing::525/60 interlaced system in slave mode vsync hsync fsync vsync polarity sub-address71[5] csync 3 4 5 6 7 fsync polarity sub-address71[4] odd field csync vsync hsync fsync 266 267 268 269 even field sub-address71[1:0] =10, 11 hsync delay sub-address 7a[7:0], 71[3:0] internal hsync reset counter 9 fig 9 : analog sync timing::rise and fall 2.37us 29.41us 27.04us 4.74us 0.148us 0.148us 63.56us ntsc pal 0.222us 0.222us 2.37us 29.63us 27.26us 4.74us 64.00us mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 10 fig 11 : sync timing::625/50 interlaced system in slave mode vsync hsync fsync vsync polarity sub-address71[5] fsync polarity sub-address71[4] odd field csync 625 1 2 3 4 csync vsync hsync fsync 313 314 315 316 even field sub-address71[1:0] =10, 11 hsync delay sub-address 7a[7:0], 71[3:0] internal hsync reset counter mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. chroma / luma encoding the dve de-multiplexes the 4:2:2 digital video data stream. the de-multiplexed y or luma samples are interpolated (2x oversampled) at the clock rate. offset compensation is then added, next any vbi signals consisting of closed-caption and vid are added to the appropriate lines, then finally composite sync pulses are added to the luma signal. (see figure 12.) de-multiplexed component color cb and cr samples are interpolated (4x oversampled) at the clock rate. interpolating simplifies the output filter and allows more accurate encoding. the dve generates the necessary subcarrier color frequency for pal or ntsc encoding from the 27mhz system clock. this color subcarrier is then modulated by the base band component color cb and cr signals to create the video chroma signal. (see figure 13.) a 7.5 ire pedestal is added for the 60hz field rate. this can be added for the 50hz field rate through serial bus control. (see sub-address register descriptions) 11 cvbs and s-video or ycbcr outputs the internal digital video signals drive 10-bit d/a converters. converter outputs are bi-directional current sources where the current is proportional to the digital data with reference to the ibias reference current. the pins cvbs/cb, y and c/cr are the respective composite, luma and chroma or y/cb/cr signal current source pins. also, each dacs can drive 75ohm load register. (see "application diagram" and "sub-address register descriptions".) bias current gain dacs can be switched off through serial bus control to reduce power consumption. both outputs of unused dacs should be connected to ground through a resister to avoid charge buildup. mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 12 212 32 470 420 340 290 162 82 32 digital y input code(16~235) 525/60 and 625/50 system 100%amplitude,100%saturation color bar 0 11 30 41 59 70 89 100 -40 ire 670 620 540 490 412 362 282 232 12 232 analog y output level(525/60 system) 100%amplitude,100%saturation color bar 0 code 1023 200 0 11 30 41 59 70 89 100 -43 ire 670 620 540 490 412 362 282 232 44 232 analog y output level(625/50 system) 100%amplitude,100%saturation color bar 0 code 1023 fig 12 : luminance output range mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 13 -59 -45 -20 20 45 59 63 ire analog c output level(525/60 system) 100%amplitude,100%saturation color bar -63 0 ? } 2 2 ? } 3 2 ? } 3 0 ? } 3 2 ? } 2 2 ? } 1 1 292 256 32 68 444 480 220 256 digital cr-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar 32 332 108 404 180 480 256 digital cb-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar 256 ? } 3 0 code 511 0 1023 -63 -48 -21.5 21.5 48 63 67 ire analog c output level(625/50 system) 100%amplitude,100%saturation color bar -67 0 ? } 2 2 ? } 3 2 ? } 3 0 ? } 3 2 ? } 2 2 ? } 1 1 ? } 3 0 code 511 0 1023 fig 13 : chrominance output range mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. closed-caption encoding closed-captioned or extended data service signals can be encoded by the dve onto output video line 21/284 (ntsc) and line 22/335 (pal). the cc data is input through the serial bus interface. two 8-bit byte data pairs are encoded for each field. there are four registers for holding the data - two bytes per field. the serial data is 7bit us-ascii msb first, proceeded by an odd parity bit. total 8-bits. (p-7-6-5-4-3-2-1-0) the dve automatically generates the required clock run in and start bit for cc encoding. (see figure 16.) when closed-captioning is enabled, the system micro processor (up) should update the cc data once each frame. the system up should also write null characters when there is no cc data to encode. it is also recommended to write cc data only to the inactive frame. field1 and field2 data are double-buffered by the frame sync falling edge of previous frame, updating frame 2 data during frame1 display and frame1 data during frame2 display. (see figures 18 for sub-address register descriptions.) copy generation managment system (cgms) encoding cgms signals can be encoded by the dve onto output video line 20 (525 / 60 for japan). cgms identification signals also identify and control the tv screen presentation mode - wide screen, letterbox and or normal -16:9 or 4:3. (see figures 16 for sub-address register descriptions.) 14 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. serial control bus control of the dve device is accomplished through the i2c-bus or spi serial bus. in i2c mode, pins sda and scl are the respective data and clock signals. device address can be 42(hex)/43(hex) or 1c(hex)/1d(hex) . slave address is chosen at reset by the state of the chipa pin signal { 0 : 42(hex)/43(hex), 1 : 1c(hex)/1d(hex) } sub-address register read and write operations are documented in the following section. in spi mode, pins so, si, sck and sel are the respective data input, output, serial clock and chip select signals. register read and write operations are documented in the following section. 15 macrovision tm copy protection when the mc44722 is enabled this features in ntsc mode , the luma and chroma signals are modified according to the macrovision tm copy protection process for pay per view (ppv) applications revision 7.01 dated sep 6th , 1996. but this feature is not supported in pal mode , so please do not use this features in pal mode. enabling and control is through the serial control bus. no parts will be sent to the customer until the customer provides motorola with written confirmation of a license, non-disclosure or waiver from macrovision tm . if your customer does not use this features, please recommend to use the mc44723 no-supported the copy-guard features. mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 16 fig 14-a : i2c-bus interface write operation timing msb d7 d6 d5 d4 d3 d2 d1 d0 lsb scl sda msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb scl sda msb d7 d6 d5 d4 d3 d2 d1 d0 lsb start chip address(write) ack sub-address data 1 data n ack ack ack stop msb d7 d6 d5 d4 d3 d2 d1 d0 lsb scl sda msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb start chip address(write) ack sub-address data 1 ack ack by mcu ack stop scl sda start chip address(read) msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb data n ack by mcu ack by mcu stop scl sda data 2 fig 14-b : i2c-bus interface read operation timing mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 17 fig 15-a : spi-bus interface write operation timing msb d7 d6 d5 d4 d3 d2 d1 d0 lsb sck si msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb sck si msb d7 d6 d5 d4 d3 d2 d1 d0 lsb start write command sub-address data 1 data n sel x sel msb x x x x x x x x lsb so (don't care) msb x x x x x x x x lsb x msb d7 x x x x x x x lsb so (don't care) msb x x x x x x x x lsb mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. msb d7 d6 d5 d4 d3 d2 d1 d0 lsb sck si msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb x x x x x x x x lsb start write command sub-address data 1 stop sck si start read command msb x x x x x x x x lsb msb x x x x x x x x lsb data n stop sck si data 2 fig 15-b : spi-bus interface read operation timing sel x msb x x x x x x x x lsb so (don't care) msb x x x x x x x x lsb x sel x msb x x x x x x x x lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb so x sel msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb so 18 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. [specifications] 19 maximum ratings dc supply voltage vdd -0.5 ~ +7.0 v input voltage, all inputs vin -1.5 ~ vdd+1.5 v output voltage, all outputs vout -0.5 ~ vdd+1.5 v dc output current, per pin iout 25 ma power dissipation pd 750 mw storage temperature tstg -65 ~ +150 ? ? electrical characteristics characteristic symbol min typ max unit power supply voltage(analog blocks) avdd 3.1 3.3 3.5 v davdd 4.75 5.0 5.25 power supply voltage(digital blocks) dvdd 3.1 3.3 3.5 v dvdd supply current(analog blocks) aicc - 30 - ma supply current(digital blocks) dicc - 170 - ma operating temperature ta 0 - 70 ? ? dac blocks characteristics(power supply 3.3v,ta=25 ? ? ? } 3 ? ? ) characteristics symbol min typ max unit other resolution - - - 10 bit integral non-linearity inl - - ? } 4.0 lsb vref = 1.1v differential non-linearity dnl - - ? } 2.0 lsb vref = 1.1v analog output voltage vyo 0.85 1.00 1.15 vp-p vref = 1.5v full scale output voltage vyfs 0.85 1.00 1.15 v zero scale output voltage vyzs - 0.0 0.1 v external load resistance r l 75 120 - ? dac blocks characteristics(power supply 5.0v,ta=25 ? ? ? } 3 ? ? ) characteristics symbol min typ max unit other resolution - - - 10 bit integral non-linearity inl - - ? } 4.0 lsb vref = 1.5v differential non-linearity dnl - - ? } 2.0 lsb vref = 1.5v analog output voltage vyo - 1.5 2.0 vp-p vref = 2v full scale output voltage vyfs - 1.5 2.0 v vref = 2v zero scale output voltage vyzs - 0.0 0.1 v external load resistance r l 75 240 - ? mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 20 tds 50 ? tdh tr tf clock input data 50 ? valid not valid not valid clock blocks characteristics characteristic symbol min typ max unit clock rate fc - 27.0 - mhz clock duty cycle dty 40 50 60 ? ? digital blocks electrical characteristics(power supply 3.3v,ta=25 ? ? ? } 3 ? ? ) characteristics symbol min typ max unit input voltage high vih 2.0 - - v low vil - - 0.8 v output voltage high voh 2.4 - - v (2.0ma) low vol - - 0.5 v input leakage current iin - ? } 2.5 - ? a hi-z leakage current ioz - ? } 20 - ? a input capacitance cin - - 20 pf load capacitance c l - - 20 pf data setup time tds 4 - - ns data hold time tdh 5 - - ns input rise time tr - - 5 ns input fall time tf - - 5 ns data delay td - - 27 ns [specifications] iic/spi-bus blocks characteristics(power supply 3.3v,ta=25 ? ? ? } 3 ? ? ) characteristics symbol ? @ min typ max uni t input voltage low v ilm - - 0.8 v input voltage high v ihm 2.3 - - v input current v im - - ? } 10 ? a sda output voltage (i om =3ma) v om - - 0.4 v output current (during acknowledge) i om 3 - - ma mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. [i2c-bus slave address 42(hex)/43(hex) or 1c(hex)/1d(hex)] mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 23 [register mapping and description] sub-address 70 : variable i/o switch (write/read) msb lsb register 70 bs-off self-sw color bar select vblk sw extsync sw default : 0000_0001(bin) f/vsync sw m/s mode1 m/s mode0 bs - off : color burst control switch on/off 0 : color burst on (default) 1 : color burst off self - sw : internal self h/v counter reset switch on / off 0 : self counter reset off (default) 1 : self counter reset on note : this mode is only valid at when 70h[1: 0] is "10(bin)" or "11(bin)". color bar select : color bar select luma chroma 0 : color bar 100% 100% 1 : color bar 100% 75% vblk sw : vertical blanking mask enabale switch on-off 0 : reject vbi information data in vertical blanking period (default) 1 : through vbi information data in vertical blanking period extsync sw : composite sync/flame sync output switch 0 : frame sync output (default) 1 : compsite sync output f/vsync sw : flame sync /vertical sync output switch 0 : vertical sync output (default) 1 : frame sync output m/s sync mode1 : master or slave sync mode m/s sync mode0 00 : 656 slave or h/v master mode 01 : 656 slave mode(no h/vsync output) (defalt) 10 : fsync/hsync slave mode 11 : vsync/hsync slave mode mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. sub-address 71 : sync control (write/read) msb lsb register 71 non-inter vbi sw h-polarity v-polarity default : 0000_0100(bin) f-polarity h- delay2 h-delay1 h-delay0 non-inter : non-interlaced mode select 0 : interlace mode (default) 1 : non-interlace mode vbi sw : vertical blanking information signal input control switch on ext pin 0 : vbi input off (default) 1 : vbi input on h-polarity : polarity of hsync 0 : negative (default) 1 : positive v-polarity : polarity of vsync 0 : negative (default) 1 : positive f-polarity : polarity of fsync 0 : field1 (odd) = low level (default) 1 : field1 (odd) = high level h-delay2 : delay on hsync with referance to dvin data in master mode h-delay1 000: + 4 clock delay h-delay0 001: + 3 clock delay 010: + 2 clock delay 011: + 1 clock delay 100: + 0 clock delay 101: - 1 clock delay 110: - 2 clock delay 111: - 3 clock delay note : this h-delay can be also related with 7a[7:0] register and can delay totally +2023 clock delay in h/v or h/fsynnc slave mode. 24 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. sub-address 72 : pal/ntsc setup (write / read) msb lsb register 72 phase-set ext i/o sw color bar setup75 625/525 pal/ ntsc2 pal/ ntsc1 default : 0000_1000(bin) ntsc (if "pal/ntsc" pin is low level) 0000_0101(bin) pal test phase-set : color sub-currier phase syncronization 0 : free running (default) 1 : 1 phase reset/8 field and 1 phase reset/4 flam tset : for test, should be "0" ext i/o sw : input/output switch on ext pin 0 : vbi input(default) 1 : csync or flame sync output color bar : internal color bar genarator control 0 : nomal operation (default) 1 : color bar genarator on (need to set color bar mode on sub-address 70[5]. ) setup75 : setup level for luminance 0 : setup level for luminunce = 0ire 1 : setup level for luminunce = 7.5ire 625/525 : control line mode 0 : 525 lines / 60 hz mode 1 : 625 lines / 50 hz mode pal/ntsc2 : subcarrier control pal/ntsc1 00 : ntsc(m) 01 : pal (bdghi) 10 : pal (m) 11 : pal (n) 25 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 26 sub-address 73: vertical blanking information luma (y) level (write only) msb lsb y7 y6 y5 y4 y3 y2 y1 y0 msb lsb u7 u6 u5 u4 u3 u2 u1 u0 register 73 register 74 sub-address 74: vertical blanking information chroma (u) level (write only) msb lsb v3 v2 v1 v0 v6 v5 v4 register 75 v7 sub-address 75: vertical blanking information chroma (v) level (write only) default : 1000_0000(bin) default : 79(dec) (ntsc) 157(dec) (pal) default : 128(dec) (ntsc) 107(dec) (pal) mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 27 sub-address 76 : signal control 1(write only) msb lsb register 76 cr cb luma cvbs dac default : 0000_0000(bin) c dac y dac cr : cr/cb signal control cb 0 : cr, cb on (default) 1 : chrominance off luma : luminance control 0 : luminance on (default) 1 : luminance off cvbsdac : d/a converter output on-off control cdac 0 : cvbs/cbdac, c/crdac, ydac output on (default) ydac 1 : cvbs/cbdac, c/crdac, ydac output off dac sw1 : 1~9-pin's d/a converter output signal control dac sw0 10 : y/cr/cb output on 00 : y/c/cvbs output on dac sw1 dac sw0 sub-address 77 : signal control 2 (write only ) msb lsb register 77 - - - - - - dac sw4 dac sw3 dac sw4 : d/a converter output signal control dac sw3 10 : y/cr/cb output on 00 : y/c/cvbs output on default : 0000_0001(bin) mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 28 h-delay10 : delay on hsync with reference to dvin data h-delay9 0000_0000_000 : hsync delay 0 delay h-delay8 to h-delay7 1111_1111_000 : hsync delay +255 delay h-delay6 h-delay5 h-delay4 h-delay3 note : this h-delay can be also related with 71[3:0] register and can delay totally +2023 delay(1111_1111_111) in h/v or h/ fsync slave mode. sub-address 7a : hsync delay control (write only) msb lsb register 7a h-dela10 h-delay9 h-delay8 h-delay7 default : 0000_0000(bin) h-delay6 h-delay5 h-delay4 h-delay3 sub-address 78~79 : sub-carrier phase control (write only) msb lsb register 78 sc-ph9 sc-ph8 sc-ph7 sc-ph6 default : 0000_0000(bin) sc-ph5 msb lsb register 79 default : 0000_0000(bin) sc-ph9 : sub-currier phase control sc-ph8 0000_0000 : sub-currier phase 0 degree (default) sc-ph7 to sc-ph6 1111_1111 : sub-currier phase 359 degree sc-ph5 sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0 sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0 - - - - - - mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. sub-address 7b : digital video input select control (write only) msb lsb register 7b - - cr_tmg 2 cr_tmg1 default : 0000_0000(bin) cr/cb_tmg2 : cr/cb clock timing delay in 16-bit digital input mode cr/cb_tmg1 00 : cr clock delay 0 clock (default) 01 : cr clock delay +1 clock 10 : cr clock delay +2 clock 11 : cr clock delay +3 clock y_tmg : y clock timing delay in 16-bit digital input mode 0 : y clock delay 0 clock (default) 1 : y clock delay +1 clock 16-bit : 16-bit multiplexed cbycry digital video inout mode input mode 0 : 8-bit cbycry digital video input mode (default) 1 : 16-bit cbycry digital video input mode y_tmg 16-bit input mode 29 cb_tmg 2 cb_tmg1 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 30 sub-address 80~82: cgms characters for field1(line20)/field2(line283) (write only) ntsc only msb lsb vid118 vid117 vid116 vid115 vid114 vid113 vid112 vid111 msb lsb vid128 vid127 vid126 vid125 vid124 vid123 vid122 vid121 register 80 register 81 msb lsb vid134 vid133 vid132 vid131 xx xx xx register 82 b8 b7 b6 b5 b4 b3 b2 b1 b16 b15 b14 b13 b12 b11 b10 b9 b20 b19 b18 b17 xx 2.235 ? 11.2 ? } 0.6 ? 49.1 ? } 0.5 ? b1 ref b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 70ire 0ire -40ire fig 16 : cgms wave form mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. sub-address 83~84 :closed caption characters/extended data for field1(line21) (write only) first byte to encode register 83 register 84 register 85 register 86 ccp118 ccb117 ccb116 ccb115 ccb114 ccb113 ccb112 ccb111 ccp128 ccb127 ccb126 ccb125 ccb124 ccb123 ccb122 ccb121 ccp218 ccb217 ccb216 ccb215 ccb214 ccb213 ccb212 ccb211 ccp228 ccb227 ccb226 ccb225 ccb224 ccb223 ccb222 ccb221 msb lsb msb lsb msb lsb msb lsb sub-address 85~86 :closed cation character/extended data for field2(line284) second byte to encode first byte to encode second byte to encode 10.50 ? } 0.5 ? 12.91 ? 4.15 ? } 0.1 ? 33.764 ? b 1 b 2 b 3 b 4 b 5 b 6 b 7 p a r i t y b 1 b 2 b 3 b 4 b 5 b 6 b 7 p a r i t y character1 character2 parity b7 b6 b5 b4 b3 b2 b1 parity b7 b6 b5 b4 b3 b2 b1 parity b7 b6 b5 b4 b3 b2 b1 parity b7 b6 b5 b4 b3 b2 b1 50ire 0ire 50ire 0ire -40ire 31 fsync sub-address 83 & 84 and 85 & 86 (previous frame data) are double-buffered by flame sync falling edge field 1 field 2 fig 17 : closed caption wave form fig 18 : closed caption data update timing default 1000_0000 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. 32 sub-address 87 :closed caption/cgms msb lsb register 87 - - - - - vbi cc2 cc1 vbi : cgms information data insertion on-off 0 : cgms information data insertion off 1 : cgms information data insertion on cc2 : closed caption/extended data for field2 encoding on-off 0 : closed caption/extended data for field2 encoding off 1 : closed caption/extended data for field2 encoding on cc1 : closed caption/extended data for field1 encoding 0 : closed caption/extended data for field1 encoding off 1 : closed caption/extended data for field1 encoding on default 000 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. %% i2c-bus slave receiver sub-address map %% 70h:[7] burst control (default 0:on) [6] self counter reset switch (default 0:off) [5] color bar select (defalut 0:luma 100% chroma 100%) [4] vertical blanking switch(default 0:off) [3] ext pin output mode select (csync:1, flame sync:0) [2] f/vsync select(default 0:vsync) [1:0] master/slave mode select(default 01:656_slave) 71h:[7] interlaced / non-interlaced (default 0:interlaced) [6] vbi input control on ext pin (default 0:off) [5] horizontal sync polarity (default 0) [4] vertical sync polarity (default 0) [3] flame sync polarity (default 0) [2:0] hsync delay control (default 100:0 clock delay) (in slave mode can use with 7a[7:0]) 72h:[7] sub-currier phase syncronaiation(default 0) [6] test mode (default 0:off) [5] ext i/o switch(defalt 1:cysnc output) [4] color bar generate(default 0:off) [3] setup level control(default 1:7.5ire) [2] 625lines50hz/525lines60hz (default set pal/ntsc pin) [1:0] pal/ntsc (default set pal/ntsc pin) 00:ntsc/m 01:pal/bghl (10:pal/m) (11:pal/n) 73h[7:0] y_register(default 80h) 74h[7:0] u_register(default 79d:ntsc/157d:pal) 75h[7:0] v_register(default 128d:ntsc/107d:pal) 76h[7] cr on/off (default 0:on) [6] cb on/off (default 0:on) [5] luma on/off(default 0:on) (default 0: on) [4] cvbs/cb dac on/off(default 0: on) [3] c/cr dac on/off(default 0: on) [2] c/cr dac on/off(default 0: on) [1] cbvs/y/c y/cr/cb output control swith (default 0 : cbvs/y/c output) [0] reserved dac yout yout c/crout c/crout cvbs/cbout cvbs/cbout yvdd cvbsvdd cvdd davdd davss ibias bias ext f/vsync hsync dvin sda/si scl/ sck $76-6 $76-7 0 0 0 $73-6 $71-7 : non_inter/interlaced $72-3 : 625line/525line 0 $76-5 $73-4 vid_gen cc_gen $80~82 $83~86 $87-3 $87-1,0 $71-4 $71-5 $71-6 sync_gen $71-2,1,0 : h_ phase $7a-7,6,5,4,3,2,1,0 copy protection bus off_set bg modulator subcarrier gen $72-1,0 $73-5 $71-7 $74~77 0 $76-5 dac 0 $76-4 dac 0 $76-3 bus tp test test pal/ntsc reset tvin demux y cb cr h,v chipa dvdd dvdd dvss dvss 77h[7:0] n.a 78h[7:0] sub-currier phase control(default 00h) 79h[1:0] sub-currier phase control(default 00) 79h:[7:2] n.a. 7a[7:0] hsync-delay control (in slave mode, is valid with 71h[2:] register) 7b[7:6] n.a 7b[5:4] cr clock timing delay in 16-bit digital input mode 7b[3:2] cb clock timing delay in 16-bit digital input mode 7b[1] y clock timing delay in 16-bit digital input mode 7b[0] 16-bit multiplexed cbycry digital input mode (default 0: 8-bit multiplexed cbycry mode) 80~82h: video id characters for field1(line20)/field2(line283) 83h[7:0] cc character1(line21) (default 'h80) 84h[7:0] cc character2(line21) (default 'h80) 85h[7:0] cc character1(line284) (default 'h80) 86h[7:0] cc character2(line284) (default 'h80) 87h[7:3] n.a. [2] cgms on/off (default 0: off) [1] cc closed caption/extended data for field2 encoding (default 0: off) [0] cc closed caption/extended data for field1 encoding (default 0: off) <<<<<<<< m-bus format >>>>>> ** write mode ** s | slave_address(w) | a | sub_address | a | data0 | a | ... | datan | a | p s start condition slave_address 42(hex) or 1c(hex) a acknowledge generated by me sub_address sub_address register data0 first data datan continued data(address is auto incremented) p stop condition <<<<<<<< spi-bus format >>>>>> ** write mode ** s | write command | sub_address | data0 | ... | datan | p s chip select on (high to low) write command 42(hex) or 1c(hex) sub_address sub_address byte data0 first data datan continued data byte(address is auto incremented) p chip select off (low to high) device-address 42, 43(hex) or 1c, 1d(hex) clock mc44722/3 vreff sel so i2c / spi 33 tp0~7 mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. [ apprication diagram ] 34 cvbs/cb hsync ext tvin dvin3 dvin4 dvin5 dvin6 dvin7 tp9 tp8 tp7 tp6 tp5 dvss dvdd tp4 mc44722/3 1 2 3 4 5 6 7 8 9 12 14 15 16 17 18 19 20 21 vreff 13 24 22 10 11 36 35 34 33 32 31 30 29 28 25 27 26 23 47 46 45 44 43 42 41 40 48 37 39 38 cvbs/cb cvbs/cbvdd y y yvdd c/cr c/cr c/crvdd davss ibias davdd chipa test so sda/si scl/sck sel dvss clock dvdd reset pal/ntsc dvin0 dvin1 dvin2 f/vsync tp3 tp2 tp1 tp0 mpeg decode r dvdd 47uf 0.01uf dvdd 47uf 0.01uf clock 10uf 100k if ntsc system = "0" else pal system = "1" mcu 47uf 0.01uf 4.7k 4.7k 1.8k 47uf 0.01uf 180 180 180 47uf 0.01uf 47uf 0.01uf 47uf 0.01uf 180 cvbs 180 y 180 c 0.01uf 1k 2k mc44722/3 rev 0.23 3/24/'97 no. this document contains information on a new product. specifications and information herein are subject to change without notice. package a detail a zd or ze min max a a1 a2 b c d e e hd he l l1 ? y zd ze - 1.70 0.05 0.15 1.40typ 0.3 0.10 11.90 11.90 13.80 13.80 0.30 0.80 0 - 1.60 1.60 0.45 0.20 12.10 12.10 0.80 14.20 14.20 0.70 1.20 10 0.10 a1 a2 e b he e hd d l1 l c ? 35 detail a unit : mm |
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